Programmable logic devices, such as field-programmable gate arrays (FPGAs), include integrated circuitry capable of being configured after manufacture. The development of configurations for these programmable logic devices typically involves many steps, known as a “design flow.” Initially, a specification for a new circuit can be transformed into a logical circuit design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical circuit design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical circuit design typically employs a Hardware Description Language (HDL), such as the Very high speed integrated circuit Hardware Description Language (VHDL). The functionality of the logical circuit design can be verified, for example, by simulating the logical circuit design with various test scenarios and verifying that the results of the simulation correspond with an expected output from the simulated logical circuit design.
The next stage of the “design flow” involves synthesizing the logical circuit design from the register transfer level into a gate-level representation, such as a netlist. The synthesis operations can include RTL synthesis, which can generate generic gates corresponding to the functionality described in the logical circuit design, and include physical synthesis, which can map the generic gates to a target programmable logic device, for example, generating a target device-specific netlist. The functionality of a gate-level netlist also can be verified, for example, by simulating the gate-level netlist with various test scenarios and verifying that the results of the simulation correspond with an expected output from the simulated gate-level netlist.
The next stage involves implementing a place-and-route process to determine the placement of elements from the gate-level netlist in the programmable logic device and the interconnections between those elements. The place-and-route process can generate a configuration file that, when downloaded to a programmable logic device, can cause the programmable logic device to implement the circuit design described by the gate-level netlist as configured by the place-and-route process.
Since simulation during the “design flow” often fails to catch all design bugs or flaws, most “design flows” include in-system debugging and validation to monitor operation of the configured programmable logic devices—typically with special debugging tools that probe and monitor an FPGA's internal signals at system-clock speed—and detect and output any aberrant behavior via a Joint Test Action Group (JTAG) port of the programmable logic devices. One type of aberrant behavior can include a meta-stable register or flop output beyond a clock-to-output time. The meta-stable output can have a floating value for an unbounded period of time before settling, oftentimes randomly, to a logic high level or logic low level. The propagation of the meta-stable output can lead to inaccurate data propagation and ultimately a system glitch or failure. Some design validation schemes can include specialized digital circuitry to compare potentially meta-stable outputs at two future times—a half-dock period after generation and a full-clock period after generation—to ascertain whether they have a different value, indicating an occurrence of a meta-stable glitch.
When aberrant behavior, like a meta-stable glitch, is detected, the circuit designers attempt to correlate the aberrant behavior to bugs in the logical circuit design, revise the logical circuit design at the RTL-level to remove the bugs, and iterate the “design flow” with the newly revised logical circuit design, i.e., re-performing synthesis, place-and-route, verification via simulation, and programmable logic device configuration. While this iterative-based design approach can validate some designs configured into an FPGA, it often comes at the cost of large footprint consumption on the FPGA under test, excessive manual intervention, and long design-time when there are a large number of iterations. In other cases, due to lack of visibility of internal signals by the special debugging tools, bugs in the design cannot be eliminated and the circuit designers re-start the “design flow” altogether.